Informatics Publishing Limited

M. Siva Kumar ¹

Affiliations
1 School of Physics, University of Hyderabad, Hyderabad 500 046, IN

Abstract

No Abstract.

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S. Inthiyaz ¹, G. Sandhya ², M. Siva Kumar ¹, M. Sridhar ¹

Affiliations
1 Department of ECE, KL University, Guntur, A.P., IN
2 KL University, IN

Abstract

Testing is an experiment in which a system is exercised and the resultant behavior is examined to make sure that the system behaves correctly. System Test tests consist of elements, test vectors, and test variables. Each of these entities to create a variety of test scenarios ranging from a simple test, which runs a series of elements once to a full parameter sweep that iterates over the values of test vectors. Test vectors and test variables map data between System Test and the model or unit under test. A Composite Video Pattern Generator is constructed, which can be used as a teaching tool in the video field as well as a laboratory instrument, useful for repairing and adjusting pattern generation of video display. This work is implemented for pattern Generator video display which is having Counters and the video pixels generated in horizontal and vertical directions. The simulation is carried out to find out the minimum set of good test vectors for the four patterns.

Keywords

Composite Video Signal, RGB Model, Test Vectors, Test Vector Generation.

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D. Arul Kumar , R. Mahesh , D. Nirmal , M. Siva Kumar

Abstract

Traffic Sign Recognition is a technology by which a vehicle is able to recognize the traffic signs put on the road e.g. “traffic light" or “Speed breakers" or "turn ahead". Traffic Sign Recognition is used to regulate traffic, warn a driver, and by Image processing. TRAFFIC SIGNS are detected and recognized in the road side, finally hardware gets work on the condition. All the detected traffic signs are intimated to the driver and some of the road signs like “Speed limit”, “Horn” etc., are get operated automatically.

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B. Murali Krishna ¹, M. Siva Kumar ¹, J. Rajesh ¹, Syed Inthiyaz ¹, J. Mounica ¹, M. Bhavani ¹, Choti Nikitha Adidela ¹

Affiliations
1 Department of Electronics and Communication Engineering, KL University, Vijayawada – 520002, Andhra Pradesh, IN

Abstract

Objective: Generally there are numerous approaches to give security information that is being imparted. However, what if the security is assured irrespective of the hackers are from the noise. The Information Security is essential concern towards each communication system. Methods/Analysis: XBee is a PAN technology based on the IEEE 802.15.4 standard. Unlike Bluetooth or wireless USB devices, XBee devices have the ability to form a mesh network between nodes. Meshing is a type of daisy chaining from one device to another. Finding: This technique allows the short range of an individual node to be expanded and multiplied, covering a much larger area. This paper describes a design of desired security for data communication by designing standard algorithm for encryption and decryption. The process occur in this module was based on encryption and decryption. The source information is generated by a bit file and this will be encrypted and is sent to destination through XBee modules. The receiving system will check the data and decrypt according to a specific algorithm and displays on the LED. Applications/Improvement: The present algorithm is implemented in Verilog HD Land simulated using Xilinx ISE simulator tool. The design is implemented on Xilinx Spartan-3 EFPGA development board. This project has applications in encoding and decoding operations for security purposes.

Keywords

Decryption, Encryption, Spartan 3E FPGA, Verilog HDL, Xgbee, Xilinx ISE Tool.

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M. Siva Kumar ¹, Syed Inthiyaz ¹, V. Narsimha Nayak ¹, M. Bhavani ¹, K. Charan Teja ¹, S. J. S. Rajesh ¹, K. Eswar Reddy ¹, G. Sruthi Keerthana ¹

Affiliations
1 Department of Electronics and Communication Engineering, KL University, Vijayawada - 522502, Andhra Pradesh, IN

Abstract

Objective: To implement high speed arithmetic systems especially conditional sum adder is used. It consists mainly conditional cells and sum cells. Method/Analysis: It contains sum and carry with input 1 and 0. These are used to reduce delay generated by the carry propagator. The advantage using conditional sum adder is addition is much faster. Finding: In this project we are going to deal with the low power conditional sum addition rule. By doing this it will basically reduce the nodes which are present internally and number of multiplexer in the adder design. By implementing this adder in cadence software the power will be reduced and the process can be done by applying clock gating and by without applying clock gating. Novelty/Improvement: For implementing this adder Verilog code is used. And this will be executed in cadence software. Because of using Verilog code, using the digital cadence software.

Keywords

Conditional Carry Addition (CCA), Clock Gating, Conditional Sum Adder (CSA), Low Power.

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